Field of the Invention
The invention relates to a power semiconductor device, and more particularly, to a power switch device having an electrostatic discharge (ESD) protection circuit.
Description of Related Art
A power switch device includes a trench power device and a planar power device, and since the trench power device can obtain a greater channel width and thereby significantly reduce channel resistance, the trench power switch device is currently more popular.
Referring to FIG. 1, FIG. 1 shows a circuit diagram of a known power switch device. The left figure is an NMOS equivalent circuit and the right figure is a PMOS equivalent circuit. A power switch device 10 includes a gate G, a source S, and a drain D. In particular, to prevent electrostatic discharge (ESD) from damaging the gate oxide layer, an ESD protection circuit can be disposed therein. Currently, the common power switch device adopts the form of a planar or trench transistor, and the source and the drain thereof are respectively located on two surfaces of the chip due to the gate of the chip surface. Therefore, the ESD protection circuit is generally disposed on the chip surface that the source is located, and the lines of the ESD protection circuit are respectively coupled to the gate and the source when connected.
Therefore, the ESD protection circuit in FIG. 1 can only be disposed between the gate G and the source S. However, if the drain located in the back of the chip is required to be connected to the ESD protection circuit, it is necessary to perform a more complex process to connect the ESD protection and the drain in the back of the chip, and ESD protection only be achieved for one of the drain and the source.